In fast digital signal processors (DSPs), particularly in those with a pronounced data path structure for the parallel data processing, a large amount of power is consumed in certain modules of the processor during the signal processing. Particularly the high demands on the signal processing speed of the processors, on the one hand, and, on the other, the demand for the processors to be used in compact appliances operated on a mobile basis and, in this case, for a long standby and operating time to be provided using a battery (storage battery) power supply contain a discrepancy in the direction of development.
To resolve this conflict, the prior art involves not only the use of fundamentally energy-saving technologies but also primarily the matching of the clock rates to the signal processing tasks in order to reduce the power consumption of the processor as a whole (speed step mode). That is to say that the clock rate is reduced in steps when the processor is in standby or has a low utilization level. An opposite sequence of steps is initiated up to the maximum possible clock rate when continuous performance demands are made on the signal processing.
This procedure for reducing the power consumption has the drawback that the efficient matching to the signal processing requested only ever occurs after a time delay. In addition, this does not achieve any specific matching to particular functional units, particularly those which are responsible for the high power consumption.
Hence, those signal processors which effect an immediate power reduction as a result of external signal allocations are not known in the prior art.
A further drawback of the known energy-saving methods is that it is not possible to shut down functional units on the basis of algorithms, which means that it is not possible to make full use of additional energy-saving effects by temporarily shutting down modules which consume a lot of power while particular algorithms are being executed in the various functional units.
Consideration is now being given to ways of improving digital signal processor shut down methods. In particular, attention is directed to shut down procedures that can be initiated in response to external signal allocations. Signal processor shut down procedures that are based on algorithms are desirable.